This invention relates to a logic integrated circuit, and more particularly to a logic circuit which uses a transister as a load element.
In various logic integrated circuits (IC) including a MOS integrated circuit etc., the development of integrated circuits having higher performances and larger integration scales or density has been desired.
Among the performance measurements of the logic circuits that are important are the switching rate at which a high (H) voltage level changes to a low (L) voltage level, or vice versa, in the logic circuit and the power consumption which is required to maintain an operation. Further performance measurements are the noise immunity etc. at which the logic circuit operates properly without erroneously responding to noise. On the other hand, from the standpoint of enhancing the performances of the integrated circuit, reducing the cost and improving the functions, it is desirable to raise the integration density. Among the circuit forms of the logic circuits used to realize such requirements, there are various circuit forms embodied in a bipolar integrated circuit and a MOS integrated circuit, and they each have advantageous features. In particular, the MOS integrated circuit has the merit of a high packaging density as compared with the bipolar integrated circuit and is adopted as a major circuit form in a large-scale integrated circuit (abbreviated to "LSI").
In the MOS integrated circuit, a large number of circuit types have heretofore been used, and they each have their merits and demerits. In general, an inverter circuit which is the basic gate of a logic circuit is arranged by connecting a load element to a single driving transistor. For the MOS integrated circuit, a MOS transistor is ordinarily employed as the load element. Various performance characteristics and features result from the sorts of load transistors, operating mechanisms, etc., and the circuit types of the MOS integrated circuit are classified in accordance with them. As the circuit types of prior-art MOS integrated circuits, there have been extensively used three sorts of circuits; an enhancement-enhancement type circuit (abbreviated hereinafter as "E/E type circuit"), an enhancement-depletion type circuit (abbreviated hereinafter as "E/D type circuit") and a complementary MOS circuit (abbreviated hereinafter as "C-MOS circuit").
The E/E type circuit is a circuit which uses enhancement-mode MOS transistors for both a driving transistor and a load transistor. Usually, the gate terminal of the load transistor 2 is fixed to a power source potential as shown in FIG. 1A. On the other hand, the E/D type circuit employs an enhancement-mode MOS transistor as a driving transistor and a depletion-mode MOS transistor as a load transistor. As shown in FIG. 1B, the gate terminal of the load transistor 2 is connected to an output terminal 3. The operations of these two circuits will be briefly described. When an input is at a low (L) level such that the driving transistor 1 is in its non-conductive ("off") state, a high (H) level appears at the output terminal 3 through the pull-up load transistor 2. In contrast, when the input is at the H level, the driving transistor 1 falls into its conductive ("on") state and short-circuits the output terminal 3 to the ground potential, so that the L level appears at the output. Thus, the inverting operation is executed. The E/E type and E/D type circuits are very simple in their circuit arrangement, since they are constructed of only MOS transistors in either the n-channel or the p-channel polarity, and they are suitable for the IC implementation and thus are extensively utilized. With these circuits, however, as is apparent from the above explanation of their operation, in order to provide an L level of sufficiently low magnitude at the output when the driving transistor is "on", the current of the load transistor needs to be set at a low magnitude at below about 1/10 of the current of the driving transistor. On the other hand, when a transient response change is considered for measuring the switching rate of the gate circuit, the shift of the driving transistor from "on" to "off" and the consequent shift of the output terminal from L to H does not take place instantly, but the output potential rises for the first time when a load capacitance, (4 in FIG. 1A) composed of several parasitic capacitances existing at the output terminal point, is charged by the current from the load transistor. At this time, in the E/E type circuit, the load current is much smaller than the "on" current of the driving transistor because of the capacitance. Accordingly, the charging process takes a very long time and governs the switching speed of the gate circuit. These circumstances are apparent from the load curves of the load elements depicted as the voltage-current characteristics of the driving transistors in FIG. 1C. In particular, it is a serious disadvantage of the E/E type circuit that the load characteristic of the E/E type circuit is downwardly convex, so the charging current becomes lower with a rise in the output potential. It is the E/D type circuit that has been improved so as to attain a high charging efficiency. Since the E/D type circuit can hold the gate-source voltage of the load transistor constant, it exhibits the load characteristic of a substantially constant current as shown in FIG. 1C and operates at higher speed.
As is apparent from the explanation of the E/E and E/D circuit operation, the load transistor is normally in the "on" state in the above E/E type or E/D type circuit. Accordingly, in the gate circuit in which the driving transistor is "on", the load current normally flows from the power source potential to the ground, and power is normally consumed in order to maintain a logical state. Especially in recent years, high-speed operation has been required along with the large-scale integration. In such circuits, the operating current level needs to be made high, which causes the power consumption to increase. Thus, power consumption has become the most influential factor limiting the integration scale.
In comparison with the foregoing E/E type and E/D type circuits, the C-MOS circuit has more ideal features as the logic circuit type to be used in 1C's. FIG. 2A shows a circuit diagram of the C-MOS circuit. This circuit is arranged so that transistors of both polarities, that is, an n-channel MOS transistor 1 and a p-channel MOS transistor 2, are symmetrically connected. An output terminal 3 is connected at a node between the drains of both the transistors, while an input terminal 5 is connected to the gate terminals of both the transistors. In operation, when the input is at the H level, the n-channel transistor 1 is "on", and the p-channel transistor 2 turns "off" at this time, so that the L level appears at the output. In contrast, when the input is at the L level, the n-channel transistor turns "off" and the p-channel transistor turns "on", so that the H level appears at the output. In this manner, in the C-MOS circuit, in either of the "on" and "off" states of the gate, one of the two transistors is "off" and a current path from the power source toward the ground level is not formed. Accordingly, the C-MOS circuit has the advantageous feature of very low power consumption. Operating currents of equal values alternately flow through the n-channel and p-channel transistors during the "on" and "off" states of the gate as illustrated in FIGS. 2B and 2C. Therefore, both the charging and discharging process of a load capacitance 4 can be performed with relatively large currents, and the C-MOS circuit is improved in switching speed. Since, however, the C-MOS circuit requires transistors of both polarities, i.e., the n-channel and the p-channel as stated above, its manufacturing process usually becomes very complicated, and a decrease in the good gate percentage, a rise in cost, etc. are inevitable.
With enhancement in the functions of integrated circuits and expansion of the integration scale thereof, the features of higher speed and higher integration density have been eagerly requested. To this end, a circuit type which has a power consumption low enough to allow a high-speed operation and to allow the high density of integration for which the manufacturing process is simple is needed.